A range of RISC-V based accelerators are available and coming to market, and there is strong potential for these to be used for High Performance Computing (HPC) workloads. However, such accelerators tend to provide bespoke programming models and APIs that require codes to be rewritten. In scientific computing, where many of the simulation code are highly complex, extensive, and written in Fortran, this is not realistic. In this extended abstract we present an approach that enables driving such architectures via Fortran, avoiding code redevelopment.
As the electric power grid increasingly hosts energy storage devices, renewable energy resources, plug-in hybrid and electric vehicles, and data centers, it is expected to benefit in the future from a multi-layer DC structure meshed within its legacy AC architecture. As such a multi-layer grid structure evolves, interconnection of DC grids with different voltage levels will become necessary. For such interconnections and for power-flow control, efficient isolated DC-DC converters are a key enabling technology. This thesis thus presents the results of an in-depth investigation into the operation, modulation, control, and performance assessment of a particular DC-DC converter configuration. The proposed DC-DC converter, which is based upon a hybrid combination of the conventional dual-active-bridge topology and the modular multi-level converter (MMC) configuration, is a potential candidate topology for interconnection of medium- and low-voltage DC grids. The thesis first introduces the circuit topology and presents the basics of operation and governing steady-state equations for the converter. Then, based on the developed mathematical model, it identifies a suitable modulation strategy for the converter bridges and submodules, as well as strategies for the regulation of the MMC submodule capacitor voltages and soft switching of the constituent semiconductor devices. The proposed converter topology offers significant benefits including galvanic isolation, utilization of the transformer’s leakage inductance, soft switching for high-frequency operation, and bidirectional power flow capability. The validity of the mathematical model, effectiveness of the proposed modulation and control strategies, and the realization of soft switching are verified through off-line simulation of a detailed circuit model as well as experiments conducted on a 1-kW experimental setup.
As the electric power grid increasingly hosts energy storage devices, renewable energy resources, plug-in hybrid and electric vehicles, and data centers, it is expected to benefit in the future from a multi-layer DC structure meshed within its legacy AC architecture. As such a multi-layer grid structure evolves, interconnection of DC grids with different voltage levels will become necessary. For such interconnections and for power-flow control, efficient isolated DC-DC converters are a key enabling technology. This thesis thus presents the results of an in-depth investigation into the operation, modulation, control, and performance assessment of a particular DC-DC converter configuration. The proposed DC-DC converter, which is based upon a hybrid combination of the conventional dual-active-bridge topology and the modular multi-level converter (MMC) configuration, is a potential candidate topology for interconnection of medium- and low-voltage DC grids. The thesis first introduces the circuit topology and presents the basics of operation and governing steady-state equations for the converter. Then, based on the developed mathematical model, it identifies a suitable modulation strategy for the converter bridges and submodules, as well as strategies for the regulation of the MMC submodule capacitor voltages and soft switching of the constituent semiconductor devices. The proposed converter topology offers significant benefits including galvanic isolation, utilization of the transformer’s leakage inductance, soft switching for high-frequency operation, and bidirectional power flow capability. The validity of the mathematical model, effectiveness of the proposed modulation and control strategies, and the realization of soft switching are verified through off-line simulation of a detailed circuit model as well as experiments conducted on a 1-kW experimental setup.
Eigenvectors of matrices on a network have been used for understanding spectral clustering and influence of a vertex. For matrices with small geodesic-width, we propose a distributed iterative algorithm in this letter to find eigenvectors associated with their given eigenvalues. We also consider the implementation of the proposed algorithm at the vertex/agent level in a spatially distributed network.
The Giskard consensus protocol is used to validate transactions and computations in the PlatON network. In this paper, we provide a rigorous specification of Giskard, suitable to serve as a reference in protocol implementation and in formal verification. Using our specification, we prove that the protocol guarantees several notable safety properties.
The interblockchain communication protocol (IBC) is an end-to-end, connection-oriented, stateful protocol for reliable, ordered, and authenticated communication between modules on separate distributed ledgers. IBC is designed for interoperation between heterogenous ledgers arranged in an unknown, dynamic topology, operating with varied consensus algorithms and state machines. The protocol realises this by specifying the sufficient set of data structures, abstractions, and semantics of a communication protocol which once implemented by participating ledgers will allow them to safely communicate. IBC is payload-agnostic and provides a cross-ledger asynchronous communication primitive which can be used as a constituent building block by a wide variety of applications.
We propose a static loop vectorization optimization on top of high level dataflow IR used by frameworks like TensorFlow. A new statically vectorized parallel-for abstraction is provided on top of TensorFlow, and used for applications ranging from auto-batching and per-example gradients, to jacobian computation, optimized map functions and input pipeline optimization. We report huge speedups compared to both loop based implementations, as well as run-time batching adopted by the DyNet framework.
All-to-all data transmission is a typical data transmission pattern in blockchain systems. Developing an optimization scheme that provides high throughput and low latency data transmission can significantly benefit the performance of those systems. In this work, we consider the problem of optimizing all-to-all data transmission in a wide area network(WAN) using overlay multicast. We prove that in a congestion-free core network model, using shallow broadcast trees with heights up to two is sufficient for all-to-all data transmission to achieve the optimal throughput allowed by the available network resources.
In this paper we present cuSten, a new library of functions to handle the implementation of 2D and batched 1D finite-difference/stencil programs in CUDA. cuSten wraps data handling, kernel calls and streaming into four easy to use functions that speed up development of numerical codes on GPU platforms. The paper also presents an example of this library applied to solve the Cahn-Hilliard equation utilizing an ADI method with periodic boundary conditions, this solver is also used to benchmark the cuSten library performance against a serial implementation.
This paper introduces a scalable and secure contract-enforcement mechanism, called Cop, which can be applied to a broad range of multi-agent systems including small and large systems, time-critical systems, and systems-of-systems. Cop enforces contracts (or protocols) via the existing Law- Governed Interaction (LGI) mechanism, coupled with a new protective layer that significantly enhances the dependability and security of such enforcement. Cop is arguably superior to the currently popular blockchain-based smart-contract mechanisms, due to its scalability, interoperability, and the breadth of the spectrum of its domain of applications.
Despite broad discussions on privacy challenges arising from fog computing, the authors argue that privacy and security requirements might actually drive the adoption of fog computing. They present four patterns of fog computing fostering data privacy and the security of business secrets, complementing existing cryptographic approaches. Their practical application is illuminated on the basis of three case studies.
A conflict-free replicated data type (CRDT) is an abstract data type, with a well defined interface, designed to be replicated at multiple processes and exhibiting the following properties: (1) any replica can be modified without coordinating with another replicas; (2) when any two replicas have received the same set of updates, they reach the same state, deterministically, by adopting mathematically sound rules to guarantee state convergence.
Modern datacenters assemble a very large number of disk drives under a single roof. Even if economic and technical factors where to make individual drives more reliable (which is not at all clear, given the commoditization of the technology), their sheer numbers combined with their ever increasing utilization in a well-balanced design makes achieving storage reliability a major challenge. In this paper, we assess the challenge of storage system reliability in the modern datacenter, and demonstrate how good disk failure prediction models can significantly improve the reliability of such systems.
We present the SC-ABD algorithm that implements sequentially consistent distributed shared memory (DSM). The algorithm tolerates that less than half of the processes are faulty (crash-stop). Compared to the multi-writer ABD algorithm, SC-ABD requires one instead of two round-trips of communication to perform a write operation, and an equal number of round-trips (two) to perform a read operation. Although sequential consistency is not a compositional consistency condition, the provided correctness proof is compositional.
This paper reports the implementation and performance evaluation of the OpenSHMEM 1.3 specification for the Adapteva Epiphany architecture within the Parallella single-board computer. The Epiphany architecture exhibits massive many-core scalability with a physically compact 2D array of RISC CPU cores and a fast network-on-chip (NoC). While fully capable of MPMD execution, the physical topology and memory-mapped capabilities of the core and network translate well to Partitioned Global Address Space (PGAS) programming models and SPMD execution with SHMEM.