The Schulze method is a voting rule widely used in practice and enjoys many positive axiomatic properties. While it is computable in polynomial time, its straight-forward implementation does not scale well for large elections. In this paper, we develop a highly optimised algorithm for computing the Schulze method with Pregel, a framework for massively parallel computation of graph problems, and demonstrate its applicability for large preference data sets. In addition, our theoretic analysis shows that the Schulze method is indeed particularly well-suited for parallel computation, in stark contrast to the related ranked pairs method. More precisely we show that winner determination subject to the Schulze method is NL-complete, whereas this problem is P-complete for the ranked pairs method.
Christian Ewert, Amrit Sharma Poudel, Mouadh Ayache
et al.
Hash functions have become a key part of standard Post-quantum cryptography (PQC) schemes, especially Sha-3 and Shake, calling arXiv:submit/7045552 [cs.AR] 3 Dec 2025 for lightweight implementation. A fault-resilient design is always desirable to make the whole PQC system reliable. We, therefore, propose a) a unified hash engine supporting Sha-3 and Shake that follows a byte-wise in-place partitioning mechanism of the so-called Keccak state, and b) an according fault detection for Keccak state protection exploiting its cube structure by deploying two-dimensional parity checks. It outperforms the state-of-the-art (SoA) regarding area requirements at competitive register-level fault detection by achieving 100% detection of three and still near 100% of higher numbers of Keccak state faults. Unlike SoA solutions, the proposed unified hash engine covers all standard hash configurations. Moreover, the introduced multidimensional cross-parity check mechanism achieves a 3.7x improvement in area overhead, with an overall 4.5x smaller fault-resilient engine design as demonstrated in ASIC and FPGA implementations. Integrated into a RISC-V environment, the unified hash engine with the integrated fault-resilient mechanism introduced less than 8% area overhead. Our approach thus provides a robust and lightweight fault-detection solution for protecting hash functions deployed in resource-constrained PQC applications.
We consider a pair of semigroups associated to a signed poset, called the root semigroup and the weight semigroup, and their semigroup rings, $R_P^\mathrm{rt}$ and $R_P^\mathrm{wt}$, respectively. Theorem 4.1.5 gives generators for the toric ideal of affine semigroup rings associated to signed posets and, more generally, oriented signed graphs. These are the subrings of Laurent polynomials generated by monomials of the form $t_i^{\pm 1},t_i^{\pm 2},t_i^{\pm 1}t_j^{\pm 1}$. This result appears to be new and generalizes work of Boussicault, Féray, Lascoux and Reiner, of Gitler, Reyes, and Villarreal, and of Villarreal. Theorem 4.2.12 shows that strongly planar signed posets $P$ have rings $R_P^\mathrm{rt}$, $R_{P^{\scriptscriptstyle\vee}}$ which are complete intersections, with Corollary 4.2.20 showing how to compute $Ψ_P$ in this case. Theorem 5.2.3 gives a Gröbner basis for the toric ideal of $R_P^{\mathrm{wt}}$ in type B, generalizing Proposition 6.4 of Féray and Reiner. Theorems 5.3.10 and 5.3.1 give two characterizations (via forbidden subposets versus via inductive constructions) of the situation where this Gröbner basis gives a complete intersection presentation for its initial ideal, generalizing Theorems 10.5 and 10.6 of Féray and Reiner.
These proceedings contain the contributions to the CPS workshop 2023 (http://www.cpsschool.eu/cps-workshop/). The CPS Workshop 2023 is an initiative of the CPS Summer School 2023 community to offer participants close contact with leading experts in the field and the opportunity to present and discuss their ideas in a dynamic and friendly setting.
Accurate branch prediction is a critical part of high performance instruction stream processing. In this paper, I present a hardware implementation of branch prediction for a RV32IM CPU, starting with static decode stage predictions and culminating in the use of BATAGE. In addition, I detail my experience writing the RTL in Hardcaml, a hardware description library for the functional programming language OCaml.
This article describes an efficient way to implement the multiplication instructions for a RISCV processor. Instead of using three predefined IP blocks for signed, unsigned and mixed multiplication, this article presents a novel extension to the Baugh-Wooley multiplication algorithm which reduces area and power consumption with roughly a factor three.
This paper aims to present a new re-configuration sequencing method for difference of read lengths that may take place as input data in which is crucial drawbacks lay impact on DNA sequencing methods.
Division algorithms have been developed to reduce latency and to improve the efficiency of the processors. Floating point division is considered as a high latency operation. This papers looks into one such division algorithm, examines the hardware block diagram and suggests an alternative path which may be cost effective.
A. E. Mironov, D. L. Carroll, J. W. Zimmerman
et al.
Cs atomic lasers, operating on the D2 line and pumped by the photoassociation of Cs-rare gas thermal collision pairs, have been examined in mixtures of Cs vapor with Ar, Kr, or Xe. Photoexcitation of the B 2Σ+ − X 2Σ+ molecular transition (i.e., the blue satellite of the D2 transition) at 836.7 nm (Cs-Ar), 841.1 nm (Cs-Kr), or 842.7 nm (Cs-Xe) yields lasers at 852.1 nm whose characteristics (optical-to-optical conversion efficiencies, pump energy threshold, and temperature dependence) are a reflection of the structure of the B 2Σ+ interatomic potential associated with each Cs-rare gas pair. Output pulse energies above 100 μJ are obtained from the Cs-Ar complex in the 493–513 K interval because of the height of the B 2Σ+ barrier in the Franck-Condon region for the pump, a molecular parameter also responsible for the robust temperature stability of the laser. Slope efficiencies (with respect to absorbed pump energy) of 17%, 12%, and 27% have been measured for Cs-Ar, Cs-Kr, and Cs-Xe pairs at 473 K, 453 K, and 453 K, respectively. The data reported here firmly link the performance of a photodissociation laser with the structure of the intermediate diatomic complex.
This paper presents an overview of the main trends in processor architecture. It starts with an analysis of the past evolution of processors and the main driving forces behind it, and then it focuses on a description of the main architectural features of current processors. Finally, it presents a discussion on some promising directions for future evolution of processor architectures.
We obtain global and local theorems on the existence of invariant manifolds for perturbations of non autonomous linear difference equations assuming a very general form of dichotomic behavior for the linear equation. The results obtained include situations where the behavior is far from hyperbolic. We also give several new examples and show that our result includes as particular cases several previous theorems.
We explore some of the properties of a subposet of the Tamari lattice introduced by Pallo, which we call the comb poset. We show that three binary functions that are not well-behaved in the Tamari lattice are remarkably well-behaved within an interval of the comb poset: rotation distance, meets and joins, and the common parse words function for a pair of trees. We relate this poset to a partial order on the symmetric group studied by Edelman.
Comparison of RISC & CISC in details, encompassing the addressing modes, evolution, definitions and characteristics. Pre - RISC design is also elaborated. Both the architectures are explained with the help of example. Analysis is made based on performance.
This chapter describes the main architectures proposed in the literature to implement the channel decoders required by the WiMax standard, namely convolutional codes, turbo codes (both block and convolutional) and LDPC. Then it shows a complete design of a convolutional turbo code encoder/decoder system for WiMax.
In this paper, we study how certain conditions can affect the transformations on the states of the memory of a strict load-store Maurer ISA, when half of the data memory serves as the part of the operating unit.
This paper presents a new dynamic power management architecture of a System on Chip. The Power State Machine describing the status of the core follows the recommendations of the ACPI standard. The algorithm controls the power states of each block on the basis of battery status, chip temperature and a user defined task priority.
A standard approach to building a fuzzy controller based on stochastic logic uses binary random signals with an average (expected value of a random variable) in the range [0, 1]. A different approach is presented, founded on a representation of the membership functions with the probability density functions.