Semantic Scholar Open Access 1988 528 sitasi

Logic verification using binary decision diagrams in a logic synthesis environment

S. Malik Albert R. Wang R. Brayton A. Sangiovanni-Vincentelli

Lihat Sumber DOI

Topik & Kata Kunci

Computer Science Mathematics

Penulis (4)

S. Malik

Albert R. Wang

R. Brayton

A. Sangiovanni-Vincentelli

Format Sitasi

APA MLA BibTeX

Malik, S., Wang, A.R., Brayton, R., Sangiovanni-Vincentelli, A. (1988). Logic verification using binary decision diagrams in a logic synthesis environment. https://doi.org/10.1109/ICCAD.1988.122451

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Informasi Jurnal

Tahun Terbit: 1988
Bahasa: en
Total Sitasi: 528×
Sumber Database: Semantic Scholar
DOI: 10.1109/ICCAD.1988.122451
Akses: Open Access ✓