Semantic Scholar Open Access 2023 23 sitasi

Low-Power Redundant-Transition-Free TSPC Dual-Edge-Triggering Flip-Flop Using Single-Transistor-Clocked Buffer

Zisong Wang Peiyi Zhao Tom Springer Congyi Zhu Jaccob Mau +3 lainnya

Abstrak

In the modern graphics processing unit (GPU)/artificial intelligence (AI) era, flip-flop (FF) has become one of the most power-hungry blocks in processors. To address this issue, a novel single-phase-clock dual-edge-triggering (DET) FF using a single-transistor-clocked (STC) buffer (STCB) is proposed. The STCB uses a single-clocked transistor in the data sampling path, which completely removes clock redundant transitions (RTs) and internal RTs that exist in other DET designs. Verified by post-layout simulations in 22 nm fully depleted silicon on insulator (FD-SOI) CMOS, when operating at 10% switching activity, the proposed STC-DET outperforms prior state-of-the-art low-power DET in power consumption by 14% and 9.5%, at 0.4 and 0.8 V, respectively. It also achieves the lowest power-delay-product (PDP) among the DETs.

Topik & Kata Kunci

Computer Science

Penulis (8)

Zisong Wang

Peiyi Zhao

Tom Springer

Congyi Zhu

Jaccob Mau

Andrew Wells

Yinshui Xia

Lingli Wang

Format Sitasi

APA MLA BibTeX

Wang, Z., Zhao, P., Springer, T., Zhu, C., Mau, J., Wells, A. et al. (2023). Low-Power Redundant-Transition-Free TSPC Dual-Edge-Triggering Flip-Flop Using Single-Transistor-Clocked Buffer. https://doi.org/10.1109/TVLSI.2023.3251286

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Informasi Jurnal

Tahun Terbit: 2023
Bahasa: en
Total Sitasi: 23×
Sumber Database: Semantic Scholar
DOI: 10.1109/TVLSI.2023.3251286
Akses: Open Access ✓