Taylor Series Interpolation-Based Direct Digital Frequency Synthesizer with High Memory Compression Ratio

A common challenge in direct digital frequency synthesizers (DDFSs) is obtaining high memory compression while maintaining good output signal purity. To address this challenge, in this paper, we present a 16-bit, quadrature direct digital frequency synthesizer (DDFS) that utilizes the second-order Taylor series polynomial interpolation in the phase-to-amplitude conversion. In this approach, the sinusoidal signal is divided into multiple segments, and for each segment, related values are stored into a look-up table (LUT). The amplitude values for each segment are calculated using the stored LUT values and the second-order Taylor series polynomial interpolation. A Python-based model was created to optimize the number of segments, and the resulting design was coded using register-transfer level VHDL. The design is synthesized and implemented on an AMD Artix 7 FPGA, and the implementation results are presented. We show that the proposed design is capable of reaching a very high memory compression ratio of 5178:1. Additionally, the design generates both sine and cosine with high spectral purity utilizing a low number of FPGA resources compared to previous work. With 107 logic slices and 3 DSP slices, the design reaches a spurious-free dynamic range (SFDR) of −102.9 dBc.