Characterization of the Power Distribution Network for Commercialized STM32s Using a Resonance Frequency Measurement Method

Power integrity is a critical aspect of microcontroller (MCU) system design. The present tendency of increasing current density and operating frequency, along with decreasing operating voltage, significantly diminishes voltage margins. Given the cost efficiency required for MCU systems, this context places important constraints on the design of the power distribution network (PDN), which directly impacts power supply noise. Therefore, characterizing the PDN is necessary. This paper introduces a cost-effective measurement and modeling method to estimate the die-package resonance frequency of the PDN, a major threat to power integrity. The method, applied to two 32-bit MCUs from STMicroelectronics with varying PDN configurations, enables the identification of the die-package resonance frequency. The results lead to the refinement of the die capacitance model for both cases, with a maximum relative error of less than 7%. The final objective is to implement the measurement system in the die in order to adjust the PDN if necessary.