Chip Design of Multithreaded and Pipelined RISC-V Microcontroller Unit

Multithreading is widely used in microcontroller unit (MCU) chips. Multithreaded hardware is composed of multiple identical single threads and provides instructions to different threads. Using the concept of thread-level parallelism (TLP), pauses are compensated for during single-thread operation to increase the throughput at the same unit. The principle of pipelined management is to use instruction-level parallelism (ILP) to split the MCU into multiple stages. When an instruction is given in a certain stage, other instructions are provided to operate in other idle stages and improve their execution efficiency. Based on the four-thread and pipelined RISC-V MCU architecture, we analyzed the instruction types of three benchmarks, i.e., Coremark, SHA, and Dijkstra. A total of 94% of the instructions use the arithmetic logic unit (ALU). Based on the executable four-thread architecture, we developed two to four RISC-V architectures with different numbers of ALUs and a dispatch algorithm. This architecture allows for the simultaneous delivery of multiple instructions, enabling parallel processing of instructions and increasing efficiency. Compared to the traditional RISC-V architecture with only one ALU, the test results showed that the instructions per clock (IPCs) of RISC-V architectures with two, three, and four ALUs increased efficiency by 76, 128.9, and 154.3%, while the area increased by 12, 22.3, and 32.6% and the static power consumption increased by 5.1, 9.2, and 13.3%. The results showed a significant improvement in performance with only a slight increase in the area. Due to the limited area of chips, a two-thread microcontroller architecture was used for the IC design and tape-out. TSMC’s 180nm process with a chip area of 1190 × 1190 μm at 133 MHz was used in this study.