DOAJ Open Access 2023

Methodology for a Low-Power and Low-Circuit-Area 15-Bit SAR ADC Using Split-Capacitor Mismatch Compensation and a Dynamic Element Matching Algorithm

William Bontems Daniel Dzahini

Abstrak

This paper presents a design methodology for a low-power, low-chip-area, and high-resolution successive approximations register (SAR) analog-to-digital converter (ADC). The proposed method includes a segmented capacitive DAC (C-DAC) to reduce the power consumption and the total area. An embedded self-calibration algorithm based on a set of trimming capacitors was applied alongside a dynamic element matching (DEM) procedure to control the inherent linearity issues caused by the process mismatch. The SAR ADC and each additional algorithm were modeled in MATLAB to show their efficiency. Finally, a simple methodology was developed to allow for the fast estimation of signal-to-noise ratios (SNRs) without any FFT calculation.

Topik & Kata Kunci

Electronic computers. Computer science Electric apparatus and materials. Electric circuits. Electric networks

Penulis (2)

William Bontems

Daniel Dzahini

Format Sitasi

APA MLA BibTeX

Bontems, W., Dzahini, D. (2023). Methodology for a Low-Power and Low-Circuit-Area 15-Bit SAR ADC Using Split-Capacitor Mismatch Compensation and a Dynamic Element Matching Algorithm. https://doi.org/10.3390/chips2010003

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Informasi Jurnal

Tahun Terbit: 2023
Sumber Database: DOAJ
DOI: 10.3390/chips2010003
Akses: Open Access ✓