DOAJ Open Access 2022

Power Limiter with PIN Diode Embedded in Cavity to Minimize Parasitic Inductance

Dong Yun Jung Kun Sik Park Jong Il Won Doohyung Cho Sungkyu Kwon +2 lainnya

Lihat Sumber DOI

Abstrak

This letter introduces a power limiter that limits the input power to protect the receiver when a large power enters the radio frequency receiver. When the power limiter receives a large power signal, a positive-intrinsic-negative (PIN) diode is turned on to limit the input power by lowering the impedance. We analyzed the characteristics of the power limiter according to the method of connecting the PIN diode in parallel with the input and output transmission lines of the power limiter. By embedding a PIN diode into the cavity and minimizing the length of the wire, a power limiter was designed and implemented to minimize parasitic inductance. In the S-band, the proposed power limiter’s insertion loss was below 0.5 dB, and the reflection loss characteristics were below 15 dB. Furthermore, it achieved an output P1dB of 21.8 dBm at 3.5 GHz.

Topik & Kata Kunci

Electrical engineering. Electronics. Nuclear engineering Electricity and magnetism

Penulis (7)

Dong Yun Jung

Kun Sik Park

Jong Il Won

Doohyung Cho

Sungkyu Kwon

Hyun Gyu Jang

Jong-Won Lim

Format Sitasi

APA MLA BibTeX

Jung, D.Y., Park, K.S., Won, J.I., Cho, D., Kwon, S., Jang, H.G. et al. (2022). Power Limiter with PIN Diode Embedded in Cavity to Minimize Parasitic Inductance. https://doi.org/10.26866/jees.2022.6.l.10

Akses Cepat

Lihat di Sumber doi.org/10.26866/jees.2022.6.l.10

Informasi Jurnal

Tahun Terbit: 2022
Sumber Database: DOAJ
DOI: 10.26866/jees.2022.6.l.10
Akses: Open Access ✓