DOAJ Open Access 2026

Area-Efficient Polynomial Multiplication Hardware Implementation for Lattice-based Cryptography

XIE Jiaxing, PU Jinwei, FANG Weitian, ZHENG Xin, XIONG Xiaoming

Abstrak

Lattice-based post-quantum cryptography algorithms demonstrate significant potential in public-key cryptography. A key performance bottleneck in hardware implementation is the computational complexity of polynomial multiplication. To address the problems of low area efficiency and memory mapping conflicts encountered in polynomial multiplication, this study proposes a polynomial multiplication structure based on Partial Number Theoretic Transform (PNTT) and a Coefficient Crossover Operation (CCO). First, the last round of the Number Theoretic Transform (NTT), coefficient multiplication, and the first round of the Inverse Number Theoretic Transform (INTT) are merged into a CCO, reducing two rounds of butterfly operations and 50% of the twiddle factor storage space; consequently, memory access overhead is lowered. Second, lightweight hardware is employed to implement modular addition, modular subtraction, division by two, and enhanced Barrett-based modular multiplication, effectively reducing the logical resource overhead. Simultaneously, the study designs a reconfigurable Processing Element (PE) array using pipeline and time-sharing multiplexing techniques, allowing each operation unit to be efficiently reconnected under different transformations. In addition, the study introduces coefficient grouping storage and special memory mapping methods in the memory mapping scheme. The efficient scheduling of data and twiddle factors is achieved by leveraging address-mapping rules, avoiding memory mapping conflicts, and achieving low-cost memory access. Finally, a First Input First Output (FIFO) structure is employed for data reorganization, which enhances data access efficiency. Experimental results show that the proposed polynomial multiplication structure reduces the Area-Time Product (ATP) of Slices and Digital Signal Processor (DSP) by over 21.7% and 61.1%, respectively, compared to existing works and has a higher area efficiency.

Penulis (1)

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XIE Jiaxing, PU Jinwei, FANG Weitian, ZHENG Xin, XIONG Xiaoming

Format Sitasi

Xiaoming, X.J.P.J.F.W.Z.X.X. (2026). Area-Efficient Polynomial Multiplication Hardware Implementation for Lattice-based Cryptography. https://doi.org/10.19678/j.issn.1000-3428.0069229

Akses Cepat

Informasi Jurnal
Tahun Terbit
2026
Sumber Database
DOAJ
DOI
10.19678/j.issn.1000-3428.0069229
Akses
Open Access ✓