112-Gb/s DSP-Based PAM-4 Transceivers for Large-Scale Ethernet Switching Systems
Abstrak
As modern ASICs integrate several hundred interconnect ports in a large package, ASIC Serdes design faces challenging performance, power, and area targets. Thanks to architectural advancements and technology scaling, a DSP-based transceiver has demonstrated better than 40-dB loss compensation with competitive power and area that enabled very large-scale Serdes integration in a single package. This article reviews two recent publications for long-reach ASIC Serdes designed in 5- and 7-nm FinFET. With detailed discussions on design challenges from major building blocks, TX/RX/PLL, a novel TX data path bandwidth extension technique by a feedback equalizer is proposed with silicon data.
Topik & Kata Kunci
Penulis (4)
Henry Park
Mohammed Abdullatif
Ehung Chen
Tamer Ali
Akses Cepat
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- 2024
- Sumber Database
- DOAJ
- DOI
- 10.1109/OJSSCS.2024.3488654
- Akses
- Open Access ✓