A Connectivity-Aware Via-Programmable DNN Processor Using a Single Photomask

This paper presents a via-programmable DNN processor architecture, the Via-Programmable Neuron Array (VPNA), designed for low-NRE and low-power AIoT applications. To enable shared base-chip layouts across diverse workloads, a connectivity-aware design ensures tile-to-tile routing under a column-wise placement rule. A <inline-formula> <tex-math notation="LaTeX">$6{\times }6$ </tex-math></inline-formula> programmable-wire structure supports task-specific data paths, and via-based ternary-weight mapping allows multiple tasks to reuse the same base chip with a single via mask. A unified bit-serial neuron circuit supports convolution and pooling operations under both neuron-serial and neuron-parallel modes, completing the functional implementation required for one-dimensional time-series DNNs. Post-layout evaluations in a 40&#x2006;nm CMOS process demonstrate sub-milliwatt power consumption and sufficient inference accuracy across representative AIoT tasks, including keyword spotting, ECG arrhythmia detection, and EEG seizure detection. Compared with prior FPGA- and ASIC-based accelerators, the proposed architecture achieves a better trade-off among low power, low NRE cost, and task-level flexibility, highlighting its potential as a scalable foundation for future ultra-low-NRE and field-programmable AIoT processors.