ChaCha20-in-Memory for Side-Channel Resistance in IoT Edge-Node Devices

IoT edge devices process the data collected, which can contain sensitive information related to the user. It is crucial to incorporate robust encryption algorithms considering the resource and power budget of these devices. In this paper, we present a power-based SCA-resistant implementation of the ChaCha20 encryption algorithm for low-end devices by utilizing memory arrays. The 10T SRAM-based implementation performs simple operations (like NAND, NOR, XOR) on the bitlines and other operations like addition/subtraction, shifting, rotation on custom-designed in-memory elements tightly coupled to sense amplifiers (SA). The design is verified for multiple test vectors to generate power consumption signatures. Welch’s t-test is performed on these signatures to demonstrate that the design is highly resistant to power-based SCA. The proposed implementation of ChaCha20 runs at 250MHz at a 1.2V supply, in 65nm Low Standby Power (LSTP) technology, achieving a speedup of around 7 times in terms of execution time compared to the ARM Cortex A9 processor.