Design Tradeoffs in Asynchronous BD Pipeline Styles of RISC-V: An FPGA-Based Comparative Study

Asynchronous processors adopt diverse pipeline styles, including linear, frequency-adaptive, selective, reduced, and combined styles, to balance performance, energy, and area. However, prior studies remain fragmented because benchmarks, tool support, and design flows differ. Those make fair comparison difficult and prevent a clear understanding of the trade-offs required for choosing pipeline styles for specific applications. Moreover, existing delay-placement flows rely on iterative synthesis or manual engineering change orders (ECOs), which are time-consuming, error-prone, and inefficient. To overcome these limitations, we introduce a morphological delay-placement constraint (MDPC), an automated delay-placement flow for bundled-data (BD) circuits on FPGAs. Compared with conventional flows, MDPC achieves single-pass timing closure with reduced slack deviation by up to 31.66% and LUT utilization by up to 5.56X, thereby enhancing performance by up to 11.94% and energy efficiency by up to 10.42%. Using MDPC, we systematically evaluate five asynchronous RISC-V pipeline styles against a synchronous baseline with typical benchmarks. The frequency-adaptive pipeline achieves the highest speed gains of 1.11%. The selective pipeline delivers the strongest energy savings of up to 65.85%. The reduced pipeline optimizes resource utilization, lowering area by up to 3.12%. The combined pipeline provides moderate improvements with energy reductions of up to 64.40%. In contrast, the linear pipeline exhibits the lowest overall efficiency, with execution slowdowns of up to 37.76%. The results reveal distinct trade-offs: the frequency-adaptive pipeline maximizes speed, the selective pipeline minimizes energy, the reduced pipeline achieves superior resource efficiency, the combined pipeline offers moderate overall gains, while the linear pipeline remains the least competitive.