DOAJ Open Access 2025

A 8.9 to 10-GHz −97.86-dBc Reference Spur Pulser-Free Continuous Charge Pump Sub-Sampling PLL With Fine-Tunable Dead-Zone Generator in 65-nm CMOS Process

Sangwon Kim Kihoon Kwon Minseo Park Jinhyuk Ahn Junseo Kim +5 lainnya

Abstrak

A sub-sampling PLL (SSPLL) with a pulser-free continuous charge pump (CCP) and a bootstrap sampling front-end has been developed and the reference spurs can be significantly suppressed by eliminating cyclic high impedance charge pump operation. A counter-based frequency-locked loop with a fine-tunable dead-zone accelerates acquisition, and the PLL path preserves precise phase tracking. The prototype circuit has been fabricated in 65-nm CMOS and operates over 8.9–10 GHz with a 40 MHz reference clock. The PLL achieves 488.01 fs RMS jitter integrated over 10 kHz–40 MHz while consuming 6.47 mW from a 1.2 V supply. The measured reference spur level is −97.86 dBc, over 25 dB lower than the pulser-based SSPLL results. The implemented architecture demonstrates that reference spur performance can be improved significantly while maintaining sub-ps jitter, making it suitable for multi-GHz applications that require stringent spur specifications.

Topik & Kata Kunci

Electrical engineering. Electronics. Nuclear engineering

Penulis (10)

Sangwon Kim

Kihoon Kwon

Minseo Park

Jinhyuk Ahn

Junseo Kim

Joonho Gil

Chulhyun Park

Yunseong Eo

Ramesh Harjani

Taehyoun Oh

Format Sitasi

APA MLA BibTeX

Kim, S., Kwon, K., Park, M., Ahn, J., Kim, J., Gil, J. et al. (2025). A 8.9 to 10-GHz −97.86-dBc Reference Spur Pulser-Free Continuous Charge Pump Sub-Sampling PLL With Fine-Tunable Dead-Zone Generator in 65-nm CMOS Process. https://doi.org/10.1109/ACCESS.2025.3639098

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