van der Waals dielectrics for threshold engineering in two-dimensional field effect transistors

Abstract Two-dimensional (2D) semiconductors are promising for next-generation field-effect transistors (FETs), but their integration into complementary-metal-oxide-semiconductors (CMOS) logic is hindered by improper threshold voltages ( $${V}_{{th}}$$ V t h ), leading to excessive power consumption. While past efforts have focused on improving gate electrostatics and near-ideal subthreshold swing ( $${SS}$$ S S ), systematic $${V}_{{th}}$$ V t h engineering in 2D FETs remains unexplored. Here, we investigate high-κ van der Waals (vdW) dielectrics including metal oxyhalides such as LaOBr, BiOBr, and BiOCl, and bimetallic thiophosphates such as LiInP2S6 (LIPS), LiInP2Se6 (LIPSe) and CuInP2S6 (CIPS), and demonstrate that bimetallic thiophosphates enable programmable and non-volatile $${V}_{{th}}$$ V t h tuning in both n-type monolayer MoS2 and p-type bilayer WSe2 FETs. Leveraging ion-mediated $${V}_{{th}}$$ V t h tuning, we realize 2D CMOS inverters with nearly three orders of magnitude reduction in static power while maintaining high switching speed. Combining experiments with industry-compatible SPICE modeling, we identify an optimal $${V}_{{th}}$$ V t h window that minimizes power with negligible delay overhead, enabling built-in power gating and improved power–performance–area metrics without additional sleep transistors.