DOAJ Open Access 2025

50 nm DrGaN in 3D monolithic GaN MOSHEMT and Silicon PMOS process on 300 mm GaN-on-Si(111)

Han Wui Then M. Radosavljevic S. Bader A. Zubair H. Vora +11 lainnya

Abstrak

We demonstrate a 50 nm DrGaN technology fabricated in a 300 mm GaN-on-Silicon process combining E-mode high-k dielectric GaN MOSHEMT with integrated 3D monolithic Si PMOS by layer transfer. The DrGaN consists of a channel-length 50 nm GaN MOSHEMT power transistor with figure-of-merit (FOM) of 1.1 (mΩ-nC)-1 and total width of 470.59 mm, integrated with a CMOS gate driver comprising a 27.19 mm wide 180 nm Si PMOS and 49.54 mm wide 130 nm GaN NMOS. In this work, we employed a gate-last 3D monolithic integration process, where the high temperature activation steps for the Si PMOS transistors are completed before the gate dielectric of the GaN MOSHEMT transistors is deposited.

Topik & Kata Kunci

Electric apparatus and materials. Electric circuits. Electric networks

Penulis (16)

Han Wui Then

M. Radosavljevic

S. Bader

A. Zubair

H. Vora

P. Koirala

M. Beumer

P. Nordeen

A. Vyatskikh

T. Hoff

J. Peck

N. Desai

H. Krishnamurthy

J. Yu

K. Ravichandran

P. Fischer

Format Sitasi

APA MLA BibTeX

Then, H.W., Radosavljevic, M., Bader, S., Zubair, A., Vora, H., Koirala, P. et al. (2025). 50 nm DrGaN in 3D monolithic GaN MOSHEMT and Silicon PMOS process on 300 mm GaN-on-Si(111). https://doi.org/10.1016/j.pedc.2024.100074

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Informasi Jurnal

Tahun Terbit: 2025
Sumber Database: DOAJ
DOI: 10.1016/j.pedc.2024.100074
Akses: Open Access ✓