Enhancing SEU tolerance efficacy in advanced FinFET FPGA devices using system-level fine-grained spatial redundancy techniques

This paper investigates the Single Event Upset (SEU) sensitivity, system-level hardening effectiveness, and potential applications of high-performance 16 nm Field Programmable Gate Arrays (FPGAs) in radiation environments. Representative circuits incorporating flip-flops and configured arithmetic logic units were specifically designed using FPGA internal resources. This integration introduces extra upset errors due to the additional utilization of arithmetic logics, contributing to a better understanding of SEU sensitivity in FPGA-based circuits within actual application designs. The irradiation tests were conducted to evaluate the SEU sensitivity of D flip-flops (DFFs) and Configuration Memories (CRAMs) under various application conditions. The results indicate that Fine-Grained (FG) Triple Modular Redundancy (TMR) circuits play a critical role in achieving high SEU tolerance, whereas general TMR hardening circuits often prove ineffective in most experiments, even with triplicated flip-flops. FG TMR circuits were developed to address the limitations of general TMR circuits, achieving SEU tolerance improvements by three orders of magnitude for output protection. Notably, FG TMR circuits showed no global signal-induced failures during proton irradiation tests. Furthermore, these system-level radiation tolerance designs present promising applications for Commercial Off-The-Shelf (COTS) devices in spaceflight and ground accelerator facility.