On chip network with increased performance for efficient wireless communication

Core systems with network transactions deployed semiconductor materials to develop wireless networks-on-chip to minimize latency with increased performance. For transmitting data from the source point towards the target point, an appropriate reconfigurable routing method has to be deployed with respect to nodes. For overhead on-chip communication that involves the linking of many cores in a single chip, congestion may occur which has to be eliminated. A marching memory arbitrator is deployed in the path that is prone to congestion which computes the port as a buffer. The static degradation of energy power utilization in the router is solved by using a Marching memory buffer. The secure communication of data can be deployed with hash, identity, and address verification blocks. The traffic is then relaxed by routing arbitrator and then data transmission is done through frequency division multiplexing in the communication channel with reconfigurable routing. The analysis of simulation results is found to have a better throughput, less latency, and reduced power consumption.