Monolithic 3D Logic Gates Based on p‐Te and n‐Bi2S3 Complementary Thin‐Film Transistors

Abstract As Moore's law approaches its limit, achieving higher device density necessitates innovative architectures, with monolithic three‐dimensional (M3D) designs emerging as a promising solution. Although numerous top‐down fabrication methods have yielded encouraging results, they often fall short of meeting the demands for large‐scale production, ultimately hindering the development of more complex, high‐performance devices. Here, a novel approach employing all thermally evaporated thin films is presented for the bottom‐up fabrication of M3D integrated logic circuits. Utilizing p‐type tellurium (Te) and n‐type bismuth sulfide (Bi2S3) as channel materials, monolithicly stacked prototypes of inverter, NAND, NOR, AND gates, SRAM, and oscillators are successfully demonstrated. This work highlights the viability of utilizing bottom‐up synthesized thin‐film transistors (TFTs) to construct sophisticated M3D logic circuits, underscoring the significance of deposition techniques such as thermal evaporation as a highly effective approach.