Binary Search‐Based Division (BSBD): A Technique for Efficient Division in Hardware

The division techniques play a key role in several computer‐implemented algorithms and applications; regrettably, they impose significant implementation constraints that hinder parallelization. The proposed binary search‐based division (BSBD) technique is inherited from the variable latency dividers, which have the potential to adjust the quotient bit’s retirement rate or the execution time in specific iterations, resulting in different conversion times across various dividend and divisor sets. This technique aims to accelerate the simple paper‐and‐pencil division by achieving significant latency reduction. This is accomplished by scanning more than one digit per iteration using the binary search algorithm on a sorted array due to the positional representation of a number. Binary search on an array is based on the divide‐and‐conquer concept, which breaks a problem into smaller subproblems that are addressed independently. A flowchart and a block diagram describing the sequence of the algorithm are included. The design is verified through simulation using the Vivado tool. Subsequently, it is synthesized and implemented on the contemporary field programmable gate array (FPGA) version, Virtex UltraScale VCU108, with extracting its performance metrics. Additionally, the design is synthesized on Synopsys and Cadence tools for its application‐specific integrated circuit (ASIC) implementation using UMC 45 nm technology. Furthermore, it is synthesized using Virtex‐4 and Kintex‐7 FPGAs to evaluate its performance against the state‐of‐the‐art, considering the utilization of the identical FPGA chips, referenced in the literature. In this context, the comparisons reveal a significant improvement in division speed. The results also suggest that an integrated processing unit is the optimal environment for this division approach. The suggested hardware implementation technique for the division operation can achieve a latency of 1.3 ns and a chip area of 2,352 μm 2 using 45 nm UMC ASIC technology, operating at a frequency range of 0.769 GHz. This makes the BSBD technique suitable for high‐speed applications. On the other hand, for the FPGA implementation, the average area reduction by the BSBD technique represents a remarkable 93.98% compared to a recent novel design in the literature. With respect to the latency, the average latency reduction achieved by the BSBD design is 140.14 ns, which represents a 58.86% decrease compared to the recent divider in the literature.