CrossRef Open Access 2023

A hardware acceleration architecture design for histogram equalization with locking features

Huijun Cao Wenbo Fan Lixiang Wang

Penulis (3)

H

Huijun Cao

W

Wenbo Fan

L

Lixiang Wang

Format Sitasi

Cao, H., Fan, W., Wang, L. (2023). A hardware acceleration architecture design for histogram equalization with locking features. https://doi.org/10.1109/icsece58870.2023.10263382

Akses Cepat

Informasi Jurnal
Tahun Terbit
2023
Bahasa
en
Sumber Database
CrossRef
DOI
10.1109/icsece58870.2023.10263382
Akses
Open Access ✓