CrossRef Open Access 2015 5 sitasi

An exercise on hardware/software codesign following the RISC model

Diya Joseph Geetika Kaur Pinaki Chakraborty

Abstrak

ABSTRACTThis paper presents an exercise to demonstrate the benefits of hardware/software codesign. A RISC processor and a high‐level language have been designed together to make best use of the features of one another. A CPU simulator, an assembler and a compiler have been implemented based on the design. The exercise is suitable for students of computer engineering and electronics engineering students nearing their graduation. © 2015 Wiley Periodicals, Inc. Comput Appl Eng Educ 24:305–312, 2016; View this article online atwileyonlinelibrary.com/journal/cae; DOI10.1002/cae.21711

Penulis (3)

Diya Joseph

Geetika Kaur

Pinaki Chakraborty

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Joseph, D., Kaur, G., Chakraborty, P. (2015). An exercise on hardware/software codesign following the RISC model. https://doi.org/10.1002/cae.21711

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Informasi Jurnal

Tahun Terbit: 2015
Bahasa: en
Total Sitasi: 5×
Sumber Database: CrossRef
DOI: 10.1002/cae.21711
Akses: Open Access ✓