Common-Mode Control and Confinement Inversion of Electrostatically Defined Quantum Dots in a Commercial CMOS Process

Confining electrons or holes in quantum dots formed in the channel of industry-standard fully depleted silicon-on-insulator CMOS structures is a promising approach to scalable qubit architectures. In this article, we present our results on a calibrated model of a commercial nanostructure using the simulation tool Quantum TCAD, along with our experimental verification of all model predictions. We demonstrate here that quantum dots can be formed in the device channel by applying a combination of a common-mode voltage to the source and drain and a back gate voltage. Moreover, in this approach, the amount of quantum dots can be controlled and modified. Also, we report our results on an effective detuning of the energy levels in the quantum dots by varying the barrier gate voltages. Given the need and importance of scaling to larger numbers of qubits, we demonstrate here the feasibility of simulating and improving the design of quantum dot devices before their fabrication based on a commercial process.