arXiv Open Access 2024

Web-Based Simulator of Superscalar RISC-V Processors

Jiri Jaros Michal Majer Jakub Horky Jan Vavra

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Abstrak

Mastering computational architectures is essential for developing fast and power-efficient programs. Our advanced simulator empowers both IT students and professionals to grasp the fundamentals of superscalar RISC-V processors, HW/SW co-design and HPC optimization techniques. With customizable processor and memory architecture, full C compiler support, and detailed runtime statistics, this tool offers a comprehensive learning experience. Enjoy the convenience of a modern, web-based GUI to enhance your understanding and skills.

Topik & Kata Kunci

cs.AR

Penulis (4)

Jiri Jaros

Michal Majer

Jakub Horky

Jan Vavra

Format Sitasi

APA MLA BibTeX

Jaros, J., Majer, M., Horky, J., Vavra, J. (2024). Web-Based Simulator of Superscalar RISC-V Processors. https://arxiv.org/abs/2411.07721

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Informasi Jurnal

Tahun Terbit: 2024
Bahasa: en
Sumber Database: arXiv
Akses: Open Access ✓