arXiv Open Access 2017

Test Generation and Scheduling for a Hybrid BIST Considering Test Time and Power Constraint

Elaheh Sadredini Mohammad Hashem Haghbayan Mahmood Fathy Zainalabedin Navabi

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This paper presents a novel approach for test generation and test scheduling for multi-clock domain SoCs. A concurrent hybrid BIST architecture is proposed for testing cores. Furthermore, a heuristic for selecting cores to be tested concurrently and order of applying test patterns is proposed. Experimental results show that the proposed heuristics give us an optimized method for multi clock domain SoC testing in comparison with the previous works.

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Penulis (4)

Elaheh Sadredini

Mohammad Hashem Haghbayan

Mahmood Fathy

Zainalabedin Navabi

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Sadredini, E., Haghbayan, M.H., Fathy, M., Navabi, Z. (2017). Test Generation and Scheduling for a Hybrid BIST Considering Test Time and Power Constraint. https://arxiv.org/abs/1711.08974

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Tahun Terbit: 2017
Bahasa: en
Sumber Database: arXiv
Akses: Open Access ✓