arXiv Open Access 2017

Cache Hierarchy Optimization

Leonid Yavits Amir Morad Ran Ginosar

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Abstrak

Power consumption, off-chip memory bandwidth, chip area and Network on Chip (NoC) capacity are among main chip resources limiting the scalability of Chip Multiprocessors (CMP). A closed form analytical solution for optimizing the CMP cache hierarchy and optimally allocating area among hierarchy levels under such constrained resources is developed. The optimization framework is extended by incorporating the impact of data sharing on cache miss rate. An analytical model for cache access time as a function of cache size is proposed and verified using CACTI simulation.

Topik & Kata Kunci

cs.AR

Penulis (3)

Leonid Yavits

Amir Morad

Ran Ginosar

Format Sitasi

APA MLA BibTeX

Yavits, L., Morad, A., Ginosar, R. (2017). Cache Hierarchy Optimization. https://arxiv.org/abs/1705.07281

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Informasi Jurnal

Tahun Terbit: 2017
Bahasa: en
Sumber Database: arXiv
Akses: Open Access ✓