arXiv Open Access 2014

Floorplanning and Topology Generation for Application-Specific Network-on-Chip

Bei Yu Sheqin Dong Song Chen Satoshi Goto

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Abstrak

Network-on-chip (NoC) architectures have been proposed as a promising alternative to classical bus-based communication architectures. In this paper, we propose a two phases framework to solve application-specific NoCs topology generation problem. At floorplanning phase, we carry out partition driven floorplanning. At post-floorplanning phase, a heuristic method and a min-cost max-flow algorithm is used to insert switches and network interfaces. Finally, we allocate paths to minimize power consumption. The experimental results show our algorithm is effective for power saving.

Topik & Kata Kunci

cs.AR

Penulis (4)

Bei Yu

Sheqin Dong

Song Chen

Satoshi Goto

Format Sitasi

APA MLA BibTeX

Yu, B., Dong, S., Chen, S., Goto, S. (2014). Floorplanning and Topology Generation for Application-Specific Network-on-Chip. https://arxiv.org/abs/1402.2462

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Informasi Jurnal

Tahun Terbit: 2014
Bahasa: en
Sumber Database: arXiv
Akses: Open Access ✓